Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
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This paper presents a novel approach to optimize the performance of a design synthesized from a given behavioral application. The high-level synthesis process is highly restricted by a precharacterized library from which components are chosen to implement operations in the behavior. Moreover, logic optimization on the register-transfer level datapath is typically limited to within the register boundaries that enclose the chosen components. It is imperative that the datapath components be carefully selected and synthesized in order to obtain a performance gain. The technique presented in this paper consists of two primary steps, application-specific macro generation and replacement, that are performed prior to high-level synthesis. The macro generation step extracts macro subgraphs from the given application graph and generates a macro component (an equivalent netlist) for each macro subgraph. Further, each macro component is optimized for performance using commercial logic synthesis tools. Using the enriched component library, a macro replacement step modifies the behavioral graph such that some subgraphs are replaced by equivalent macros. The replacement step attempts to replace subgraphs such that the design latency is minimized. The modified behavioral graph along with the enriched component library is then taken through high-level, logic and layout synthesis. Experiments on DSP benchmarks show that the macro based synthesis process achieves significant improvement in design performance as opposed to the traditional design process. We have developed an automated performance-optimization framework that is only limited by the optimization capability of backend tools.