Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models

Authors:
Qiwei Jin;David B. Thomas;Wayne Luk;Benjamin Cope
Affiliations:
Department of Computing, Imperial College, London, UK SW7 2AZ;Department of Computing, Imperial College, London, UK SW7 2AZ;Department of Computing, Imperial College, London, UK SW7 2AZ;Circuits and Systems Group, Department of Electrical and Electronic Engineering, Imperial College, London, UK SW7 2AZ
Venue:
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2008

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Abstract

This paper explores the application of reconfigurable hardware to the acceleration of financial computations involving binomial-tree pricing models. A parallel pipelined architecture capable of computing multiple binomial trees is presented, which can deal with concurrent requests for option valuations. The architecture is mapped into an xc4vsx55 FPGA. Our results show that an FPGA implementation with fixed-point arithmetic at 87.4MHz can run over 250 times faster than a Core2 Duo processor at 2.2GHz, and more than two times faster than an nVidia Geforce 7900GTX processor with 24 pipelines at 650MHz.