Implementation of the Longstaff and Schwartz American Option Pricing Model on FPGA

Authors:
Xiang Tian;Khaled Benkrid
Affiliations:
The University of Edinburgh, School of Engineering, Edinburgh, UK EH9 3JL;The University of Edinburgh, School of Engineering, Edinburgh, UK EH9 3JL
Venue:
Journal of Signal Processing Systems
Year:
2012

Citing 6
Cited 1

Random number generation and quasi-Monte Carlo methods

Random number generation and quasi-Monte Carlo methods
Numerical recipes in C (2nd ed.): the art of scientific computing

Numerical recipes in C (2nd ed.): the art of scientific computing
Primal-Dual Simulation Algorithm for Pricing Multidimensional American Options

Management Science
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models

ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation

Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Hardware generation of arbitrary random number distributions from uniform distributions via the inversion method

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Monte Carlo simulation of the Ising model on FPGA

Journal of Computational Physics

Quantified Score

Hi-index	0.00

Visualization

Abstract

American style options are widely used financial products, whose pricing is a challenging problem due to their path dependency characteristic. Finite difference methods and tree-based methods can be used for American option pricing. However, the major drawback of these methods is that they can often only handle one or two sources of uncertainty; for more state variables they become computationally prohibitive, with computation times typically increasing exponentially with the number of state variables. Alternative solutions are the extended Monte Carlo methods, such as the Least-Squares Monte Carlo (LSMC) method suggested by Longstaff and Schwartz, which uses of regression to estimate continuation values from simulated paths. In this paper, we present an FPGA hardware architecture for the acceleration of the LSMC method, with Quasi-Monte Carlo path generation. Our FPGA hardware implementation on a Xilinx Virtex-4 XC4VFX100 chip achieves 25脳 and 18脳 speed-ups in the path generation and regression steps, respectively, compared to an equivalent pure software implementation captured in C++ and run on an Intel Xeon 2.8 GHz CPU. This provides overall speed-up of 20脳 compared to a CPU-based implementation. Power measurements also show that our FPGA implementation is 54脳 more energy efficient than the pure software implementation.