SUIF: an infrastructure for research on parallelizing and optimizing compilers
ACM SIGPLAN Notices
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VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Convex Optimization
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Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally-intensive applications can be specified. Field-Programmable Gate Arrays (FPGAs) are becoming adopted as a computational platform by the high-performance computing community, but there are challenges to extract maximum performance from these devices. Unlike other approaches, our focus is on data memory organisation and input-output bandwidth considerations, which are the typical stumbling block of existing hardware compilation schemes. We describe our approaches, which are based on formal optimization techniques, and present some results showing the advantage of exposing the interaction between data memory system design and parallelism extraction to the compiler.