PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
A DAG-based design approach for reconfigurable VLIW processors
DATE '99 Proceedings of the conference on Design, automation and test in Europe
IEEE Transactions on Computers
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Automatic generation of application specific processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
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ARISE introduces a systematic approach to extend once a processor to support thereafter the coupling of an arbitrary number of Custom Computing Units (CCUs). A CCU, hardwired or reconfigurable, can be utilized in a hybrid, tight and/or loose, model of computation. By selecting the appropriate model for each part of the application, the complete application space can be considered for acceleration, resulting to significant performance improvements. To support these features ARISE proposes: i) a machine organization, ii) a set of Instruction Set Extensions (ISEs), and iii) a micro-architecture. To evaluate our proposal, a MIPS processor is extended with the ARISE infrastructure and implemented on an FPGA. Results show that the ARISE infrastructure can easily fit into the timing model of the processor. A set of benchmarks is mapped on the evaluation machine and it is proved that exploiting the hybrid model of computation, performance improvements of up to 68% are achieved compared to the case when only one model is supported. This results to significant application speedups from 2.4x up to 4.8x.