A progress report on SPUR: February 1, 1987
ACM SIGARCH Computer Architecture News
Tags and type checking in LISP: hardware and software approaches
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
RISCs vs. CISCs for Prolog: a case study
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Measurement and evaluation of the MIPS architecture and processor
ACM Transactions on Computer Systems (TOCS)
A simple interprocedural register allocation algorithm and its effectiveness for LISP
ACM Transactions on Programming Languages and Systems (TOPLAS)
Efficient macro-code emulation in hardwired pipelined processors
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
The impact of code density on instruction cache performance
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Run-time checking in Lisp by integrating memory addressing and range checking
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Trap architectures for Lisp systems
LFP '90 Proceedings of the 1990 ACM conference on LISP and functional programming
Tempest and typhoon: user-level shared memory
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
Tempest and typhoon: user-level shared memory
25 years of the international symposia on Computer architecture (selected papers)
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
LISP on a reduced-instruction-set-processor
LFP '86 Proceedings of the 1986 ACM conference on LISP and functional programming
A study of LISP on a multiprocessor preliminary version
ACM SIGPLAN Lisp Pointers
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The SPUR microprocessor has a 40-bit tagged architecture designed to improve its performance for Lisp programs. Although SPUR includes just a small set of enhancements to the Berkeley RISC-II architecture, simulation results show that with a 150-ns cycle time SPUR will run Common Lisp programs at least as fast as a Symbolies 3600 or a DEC VAX 8600. This paper explains SPUR's instruction set architecture and provides measurements of how certain components of the architecture perform.