Computer
Register allocation in the SPUR Lisp compiler
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Evaluation of the SPUR Lisp architecture
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
An in-cache address translation mechanism
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
IEEE Transactions on Computers
A trace-driven analysis of the UNIX 4.2 BSD file system
Proceedings of the tenth ACM symposium on Operating systems principles
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Caching in the Sprite Network File System
Caching in the Sprite Network File System
Process Migration in the Sprite Operating System
Process Migration in the Sprite Operating System
Curare: Restructuring Lisp Programs For Concurrent Execution
Curare: Restructuring Lisp Programs For Concurrent Execution
Estimating Performance of Single Bus, Shared Memory Multiprocessors
Estimating Performance of Single Bus, Shared Memory Multiprocessors
TLB For Free: In-Cache Address Translation For A Multiprocessor
TLB For Free: In-Cache Address Translation For A Multiprocessor
Prefix Tables: A Simple Mechanism for Locating Files
Prefix Tables: A Simple Mechanism for Locating Files
Proceedings of CS292i: Implementation of VLSI Systems
Proceedings of CS292i: Implementation of VLSI Systems
Power and Ground Requirements for a High-speed 32 Bit Computer Chip
Power and Ground Requirements for a High-speed 32 Bit Computer Chip
Design and Implementation of An Integrated Snooping Data Cache
Design and Implementation of An Integrated Snooping Data Cache
Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses
Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses
The Sprite Remote Procedure Call System
The Sprite Remote Procedure Call System
Functional Specification and Simulation of a Floating Point
Functional Specification and Simulation of a Floating Point
Virtual Memory for the Sprite Operating System
Virtual Memory for the Sprite Operating System
The SPUR Instruction Unit: An On-Chip Instruction Cache Memory
The SPUR Instruction Unit: An On-Chip Instruction Cache Memory
SPUR Coprocessor Interface Description
SPUR Coprocessor Interface Description
Data Path Design Considerations for a High Performance VLSI Multiprocessor
Data Path Design Considerations for a High Performance VLSI Multiprocessor
Special- or General-Purpose Hardware for Prolog: A Comparison
Special- or General-Purpose Hardware for Prolog: A Comparison
SPUR Memory System Architecture
SPUR Memory System Architecture
Aspects of cache memory and instruction buffer performance
Aspects of cache memory and instruction buffer performance
Simulation analysis of data-sharing in shared memory multiprocessors
Simulation analysis of data-sharing in shared memory multiprocessors
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