Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses

  • Authors:

  • Randy H. Katz;Susan J. Eggers;Garth A. Gibson;Paul M Hansen;Mark D Hill;J. M. Pendleton;Scott A Ritchie;George S. Taylor;David A. Wood;David A. Patterson

  • Affiliations:

  • -;-;-;-;-;-;-;-;-;-

  • Venue:
  • Memory Hierarchy Aspects of a Multiprocessor RISC: Cache and Bus Analyses
  • Year:
  • 1985

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Abstract

We describe the memory system design of a tightly-coupled multiprocessor. Each processor node consists of a VLSI RISC processor, a VLSI cache controller, cache data RAMs, and a standard bus. We show that adequate performance can be achieved only if the processor has an on-chip instruction buffer and a large (64KB-256KB) local instruction and data cache. Ways of reducing the number of cache tags and the effects of various implementation alternatives for where to perform virtual memory translation are also described.