Structure handling in data-flow systems
IEEE Transactions on Computers - The MIT Press scientific computation series
VLSI array processors
Incorporating data flow ideas into von neumann processors for parallel execution
IEEE Transactions on Computers
Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Dataflow Computing Models, Languages, and Machines for Intelligence Computations
IEEE Transactions on Software Engineering - Special Issue on Artificial Intelligence in Software Applications
An architecture of a dataflow single chip processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Can dataflow subsume von Neumann computing?
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Discrete-time signal processing
Discrete-time signal processing
Multiprocessor performance
Executing a Program on the MIT Tagged-Token Dataflow Architecture
IEEE Transactions on Computers
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
IEEE Transactions on Computers
Measuring parallel processor performance
Communications of the ACM
Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
Architectures for statically scheduled dataflow
Journal of Parallel and Distributed Computing - Special issue: data-flow processing
ICS '90 Proceedings of the 4th international conference on Supercomputing
Dataflow computer development in Japan
ICS '90 Proceedings of the 4th international conference on Supercomputing
Supercomputing with transputers—past, present and future
ICS '90 Proceedings of the 4th international conference on Supercomputing
Monsoon: an explicit token-store architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
APRIL: a processor architecture for multiprocessing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Pipelined Data Parallel Algorithms-I: Concept and Modeling
IEEE Transactions on Parallel and Distributed Systems
Pipelined Data Parallel Algorithms-II: Design
IEEE Transactions on Parallel and Distributed Systems
A COMPILER FOR THE MIT TAGGED-TOKEN DATAFLOW ARCHITECTURE
A COMPILER FOR THE MIT TAGGED-TOKEN DATAFLOW ARCHITECTURE
IEEE Transactions on Software Engineering
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An experimental approach is chosen to investigate the performance of a fine-grained dataflow architecture for numerically intensive digital signal processing (DSP) applications. The focus is on the behavior of pipelined data-parallel algorithms. However, the granularity of the high-level language programming blocks is not explicitly optimized to balance computation and communication; a natural and logical fine-grained decomposition of problems is used instead. The authors interpret their empirical data by means of parameters such as a number of instructions per generic unit of computation, a density of precedence relations, and a serial fraction. The performance and limitations of fine-grained general-purpose dataflow computing are discussed.