Toward a dataflow/von Neumann hybrid architecture
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Two fundamental issues in multiprocessing
4th International DFVLR Seminar on Foundations of Engineering Sciences on Parallel Computing in Science and Engineering
An architecture of a dataflow single chip processor
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Can dataflow subsume von Neumann computing?
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
The EPSILON-2 multiprocessor system
Journal of Parallel and Distributed Computing - Special issue: data-flow processing
A novel high-speed memory organization for fine-grain multi-thread computing
PARLE '91 Proceedings on Parallel architectures and languages Europe : volume I: parallel architectures and algorithms: volume I: parallel architectures and algorithms
Towards an efficient hybrid dataflow architecture model
PARLE '91 Proceedings on Parallel architectures and languages Europe : volume I: parallel architectures and algorithms: volume I: parallel architectures and algorithms
Thread-based programming for the EM-4 hybrid dataflow machine
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
T: a multithreaded massively parallel architecture
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
I/O issues in a multimedia system
Computer
ICS '90 Proceedings of the 4th international conference on Supercomputing
Monsoon: an explicit token-store architecture
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Advanced Computer Architectures
Advanced Computer Architectures
KUMP/D: the Kyushu University multi-media processor
CAMP '95 Proceedings of the Computer Architectures for Machine Perception
Fine-grain multi-thread processor architecture for massively parallel processing
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Parallel implementation of a real-time high dynamic range video system
Integrated Computer-Aided Engineering
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There are two fundamental problems to be solved in any scalable computer system: tolerate and hide latency of remote accesses, and, tolerate and hide idling due to synchronization among parallel processes. Architectures which can not solve these issues will fail in building large-scale parallel processing systems. One possible solution for tolerating memory and synchronization latency is the introduction of threads and fast context switching mechanism among threads. Systems which support this technique are called multithreaded systems. Multimedia applications usually require large computing power and thus, massivelly parallel systems are good candidates for such tasks. Additionally, multimedia applications usually involve the processing of huge amount of data (e.g. audio or video information), therefore both the classical shared or distributed memory parallel systems may be inadequate for fulfilling all the needs. Finally, multimedia applications (e.g. image processing) in some cases may require other computing model than current commodity RISC processors can provide. A range of multithreaded architectures can be idealistic for multimedia applications, which is massively parallel, has distributed memory for the sake of scalability. Such architectures, which support remote memory accesses, may be a proper combination of different computing models, e.g. von Neumannn and dataflow ones. In this paper, the design space of multithreaded architectures is introduced, and a certain architecture, called KUMP/D (Kyushu University Multimedia Processor on Datarol-II) is described. It is also shown how a multithreaded architecture can be built in a short design cycle by using a commercial high-end microprocessor and easily programmable hardware devices.