Executing compressed programs on an embedded RISC architecture
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Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
IEEE Micro
Limited Bandwidth to Affect Processor Design
IEEE Micro
Compression of Embedded System Programs
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
A DSP-enhanced 32-bit embedded microprocessor
Journal of Embedded Computing - Selected papers of EUC 2005
A DSP-Enhanced 32-bit embedded microprocessor
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
A low-power DSP-enhanced 32-bit EISC processor
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
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In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded microprocessor systems. The architecture exhibits an efficient fixed length 16-bit instruction set with short length offset and immediate operands. The offset and immediate operands can be extended to 32 bits via the operation of an extension flag.The code density of the EISC instruction set and its memory transfer performance is shown to be significantly higher than current architectures making it a suitable candidate for the next generation of embedded computer systems.The compact EISC instruction set introduces data dependencies that seemingly limit deep pipeline and superscalar implementations. This paper suggests a mechanism by which these dependencies might be removed in hardware.