Instruction-processing optimization techniques for VLSI microprocessors
Instruction-processing optimization techniques for VLSI microprocessors
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
High-performance extendable instruction set computing
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements
IEEE Transactions on Computers
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EISC (Extendable Instruction Set Computer) is a compressed code architecture developed for embedded applications and has higher code density than its competing architectures. In this paper, we propose a low-power DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the deficits, of the EISC architecture to accelerate DSP applications while adding relatively low hardware overhead. Our simulation results show that the proposed DSP-enhanced processor reduces the execution time of the considered DSP kernels by 77.6% and the MP3 applications by 30.9%. The proposed DSP enhancements cost approximately 10300 gates (18%) and do not increase the clock frequency. While the high code density of EISC would be of great advantage to a low-power embedded system, the proposed DSP enhancement could increase its power consumption by 16.9%. We show that a set of supports for power management could reduce the power consumption by 65.5%. The proposed processor has been embedded in an SoC for video processing and proven in silicon.