Instruction-processing optimization techniques for VLSI microprocessors
Instruction-processing optimization techniques for VLSI microprocessors
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
High-performance extendable instruction set computing
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements
IEEE Transactions on Computers
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EISC (Extendable Instruction Set Computer) is a compressed code architecture developed for embedded applications. In this paper, we propose a DSP-enhanced embedded microprocessor based on the 32-bit EISC architecture. We present how we could exploit the special features, and how we could overcome the weaknesses, of the EISC architecture to accelerate DSP applications with a relatively low hardware overhead. Our simulations and experiments show that the proposed DSP-enhanced processor reduces the average execution times of the DSP kernels and DSP applications considered in this work, by 42.5% and 31.3% respectively. The proposed DSP enhancements cost about 10300 gates and do not affect the operating frequency of the processor. The proposed DSP-enhanced processor has been embedded in an SoC for video processing and proven in silicon.