Traffic-Specific Interconnection Networks for Multicomputers
IEEE Transactions on Computers
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
The Named-State Register File: Implementation and Performance
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
A stack addressing scheme based on windowing
ACM SIGARCH Computer Architecture News
A Tale of Two Processors: Revisiting the RISC-CISC Debate
Proceedings of the 2009 SPEC Benchmark Workshop on Computer Performance Evaluation and Benchmarking
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
A rapid turnaround design of a high speed VLSI search processor
Integration, the VLSI Journal
Typed assembler for a RISC crypto-processor
ESSoS'12 Proceedings of the 4th international conference on Engineering Secure Software and Systems
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A processor architecture attempts to compromise between the needs of programs hosted on the architecture and the performance attainable in implementing the architecture. The needs of programs are most accurately reflected by the dynamic use of the instruction set as the target for a high level language compiler. In VLSI, the issue of implementation of an instruction set architecture is significant in determining the features of the architecture. Recent processor architectures have focused on two major trends: large microcoded instruction sets and simplified, or reduced, instruction sets. The attractiveness of these two approaches is affected by the choice of a single-chip implementation. The two different styles require different tradeoffs to attain an implementation in silicon with a reasonable area. The two styles consume the chip area for different purposes, thus achieving performance by different strategies. In a VLSI implementation of an architecture, many problems can arise from the base technology and its limitations. Although circuit design techniques can help alleviate many of these problems, the architects must be aware of these limitations and understand their implications at the instruction set level.