Performance and evaluation of LISP systems
Performance and evaluation of LISP systems
Global register allocation at link time
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Lisp on a reduced-instruction-set processor: characterization and optimization
Lisp on a reduced-instruction-set processor: characterization and optimization
Reduced instruction set computers
Communications of the ACM - Special section on computer architecture
Readings in computer architecture
Performance of various computers using standard linear equations software in a Fortran environment
ACM SIGARCH Computer Architecture News
A simple interprocedural register allocation algorithm and its effectiveness for LISP
ACM Transactions on Programming Languages and Systems (TOPLAS)
Code Optimization Across Procedures
Computer
Data buffering: run-time versus compile-time support
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Inline function expansion for compiling C programs
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
Mache: no-loss trace compaction
SIGMETRICS '89 Proceedings of the 1989 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Register allocation across procedure and module boundaries
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Architectural support for reduced register saving/restoring in single-window register files
ACM Transactions on Computer Systems (TOCS)
Mapping concurrent programs to VLIW processors
PPOPP '91 Proceedings of the third ACM SIGPLAN symposium on Principles and practice of parallel programming
Architectural support for register allocation in the presence of aliasing
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
CCG: a prototype coagulating code generator
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Flexible register management for sequential programs
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Experience with a software-defined machine architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
Unexpected side effects of inline substitution: a case study
ACM Letters on Programming Languages and Systems (LOPLAS)
Interprocedural optimization: eliminating unnecessary recompilation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Accurate static branch prediction by value range propagation
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
OS and compiler considerations in the design of the IA-64 architecture
ACM SIGPLAN Notices
OS and compiler considerations in the design of the IA-64 architecture
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Interprocedural register allocation for RISC machines
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
A Comparison of RISC Architectures
IEEE Micro
IEEE Micro
A stack addressing scheme based on windowing
ACM SIGARCH Computer Architecture News
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Performance and security lessons learned from virtualizing the alpha processor
Proceedings of the 34th annual international symposium on Computer architecture
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A large register set can be exploited by keeping variables and constants in registers instead of in memory. Hardware register windows and compile-time or link-time global register allocation are ways to do this. A measure of the effectiveness of any of these register management schemes is how thoroughly they remove loads and stores. This measure must also count extra loads and stores executed because of window overflow or conflicts between procedures.By combining profiling, instrumentation, and in-line simulation, we measured the effectiveness of several register management schemes. These included compile-time and link-time schemes for allocating registers, and register window schemes using fixed-size or variable-sized windows. Link-time allocation based on profile information was the clear winner in some cases and did about as well as windows in the rest. Even link-time allocation based on an estimated profile was about as good as windows. Variable-sized windows sometimes did better than fixed-sized windows, but the difference was usually small.Register windows require extra logic in the data path, which may slow the machine cycle slightly, and often use more chip real estate for additional registers. Proponents of windows suppose that they trade these drawbacks for a reduction in the number of memory references they must make. Our results show that this tradeoff should be made the other way. Keep the hardware simple, because a link-time register allocator can nearly duplicate the improvement in memory reference frequency. Then the cycle time can be as small as possible, resulting in faster programs overall.