Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Detecting conflicts between structure accesses
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Register windows vs. register allocation
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
CRegs: a new kind of memory for referencing arrays and pointers
Proceedings of the 1988 ACM/IEEE conference on Supercomputing
Fast interprocedual alias analysis
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Advances in Computer Architecture
Advances in Computer Architecture
A precise inter-procedural data flow algorithm
POPL '81 Proceedings of the 8th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An integrated memory management scheme for dynamic alias resolution
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Tolerating data access latency with register preloading
ICS '92 Proceedings of the 6th international conference on Supercomputing
Reducing memory traffic with CRegs
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Dynamic memory disambiguation using the memory conflict buffer
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References
IEEE Transactions on Computers
The store-load address table and speculative register promotion
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Speculative register promotion using Advanced Load Address Table (ALAT)
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Recovery code generation for general speculative optimizations
ACM Transactions on Architecture and Code Optimization (TACO)
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High performance computer architectures use registers to provide high speed access to data operands, to provide short names for operands, and to reduce memory traffic for accesses to these operands. The possibility of aliasing in a program segment reduces the quality of code that a compiler can produce by necessitating that memory and register copies of variables that have been allocated to registers be kept consistent. A hardware support mechanism is presented that permits all classes of data objects, including dynamically allocated objects and array elements, to be held in registers without consideration of possible aliases and without requiring that the generated code maintain consistency between register and memory copies of variables. Use of this approach permits programs to benefit from the speed advantages and reduced memory traffic associated with register storage, obviates the need to collect aliasing information for use in register allocation, and reduces instruction traffic by eliminating code used solely to maintain register-memory consistency. The support hardware can be implemented using known hardware technology and without increasing the cycle time of the processor.