Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Interprocedural dependence analysis and parallelization
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
The refined-language approach to compiling for parallel supercomputers
The refined-language approach to compiling for parallel supercomputers
Register allocation via usage counts
Communications of the ACM
The dream of a lifetime: A lazy variable extent mechanism
LFP '80 Proceedings of the 1980 ACM conference on LISP and functional programming
Dependence analysis for subscripted variables and its application to program transformations
Dependence analysis for subscripted variables and its application to program transformations
Architectural support for register allocation in the presence of aliasing
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
An integrated memory management scheme for dynamic alias resolution
Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Tolerating data access latency with register preloading
ICS '92 Proceedings of the 6th international conference on Supercomputing
Reducing memory traffic with CRegs
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Dynamic memory disambiguation using the memory conflict buffer
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Out-of-order vector architectures
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
The store-load address table and speculative register promotion
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Load and store reuse using register file contents
ICS '01 Proceedings of the 15th international conference on Supercomputing
Speculative register promotion using Advanced Load Address Table (ALAT)
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
| Hi-index | 0.00 |
Often, pointer and subscripted array references touch memory locations for which there are several possible aliases, hence these references cannot be made from registers. Although conventional caches can increase performance somewhat, they do not provide many of the benefits of registers, and do not permit the compiler to perform many optimizations associated with register references. The CReg (pronounced “C-Reg”) mechanism combines the hardware structures of cache and registers to create a new kind of memory structure, which can be used either as processor registers or as a replacement for conventional cache memory. By permitting aliased names to be grouped together, CRegs resolve ambiguous alias problems in hardware, resulting in more efficient execution than even the combination of conventional registers and cache can provide.This paper discusses both the conceptual CReg hardware structure and the compiler analysis and optimization techniques to manage that structure.