Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
Computer
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ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
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ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
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Communications of the ACM - Special section on computer architecture
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Simulation Analysis Data Sharing in Shared Memory Multiprocessors
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SIGMETRICS '93 Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems
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ACM Transactions on Computer Systems (TOCS)
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IEEE Transactions on Computers
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International Journal of High Performance Computing and Networking
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The important factors building a model of coherency overhead for a single-bus, shared memory multiprocessor are analyzed. Three architectural features are examined: the size of the coherency block, the cache size, and the type of bus operation used to carry out a particular coherency function. The experiments judge the effect of each architectural parameter on model accuracy by selectively including it in a base model and then comparing the model's predictions of coherency overhead to the results of detailed multiprocessor simulations. The results indicate that coherency block size is critical to include in a model of coherency overhead. This improves the accuracy of the base model by a factor of approximately 5-50, depending on the application. Cache size and the type of coherency-related bus operation are less important, contributing a 1.5% (for 128 kbyte caches) and 6% improvement, respectively, averaged over all traces.