Memory-reference characteristics of multiprocessor applications under MACH
SIGMETRICS '88 Proceedings of the 1988 ACM SIGMETRICS conference on Measurement and modeling of computer systems
ACM Transactions on Computer Systems (TOCS)
Shared Block Contention in a Cache Coherence Protocol
IEEE Transactions on Computers
Modeling the performance of limited pointers directories for cache coherence
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Simplicity Versus Accuracy in a Model of Cache Coherency Overhead
IEEE Transactions on Computers
Effects of cache coherency in multiprocessors
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
Performance prediction for random write reductions: a case study in modeling shared memory programs
SIGMETRICS '02 Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Parallel program performance prediction using deterministic task graph analysis
ACM Transactions on Computer Systems (TOCS)
A methodology for detailed performance modeling of reduction computations on SMP machines
Performance Evaluation - Performance modelling and evaluation of high-performance parallel and distributed systems
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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This paper develops a data reference modeling technique to estimate with high accuracy the cache miss ratio in cache-coherent multiproeessors. The technique involves analyzing the dynamic data referencing behavior of parallel algorithms. Data referenee modeling first identifies different types of shared data blocks accessed during the execution of a parallel algorithm, then captures in a few parameters the cache behavior of each shared block as a function of the problem size, number of processors, and cache line size, and finally constructs an analytical expression for each algorithm to estimate the cache miss ratio. Because the number of processors, problem size, and cache line size are included as parameters, the expression for the each miss ratio can be used to predict the performance of systems with different configurations. Six parallel algorithms are studied, and the analytical results compared against previously published simulation results, to establish the confidence level of the data reference modeling technique. It is found that the average prediction error for four out of six algorithms is within five percent and within ten percent for the other two. The paper also derives from the model several results on how cache miss rates scale with system size.