The ultimate RISC

  • Authors:
  • Douglas W. Jones

  • Affiliations:
  • Department of Computer Science, University of Iowa, Iowa City, Iowa

  • Venue:
  • ACM SIGARCH Computer Architecture News
  • Year:
  • 1988

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Abstract

Reduced instruction set computer (RISC) architectures have attracted considerable interest during the past decade. The ultimate RISC architecture presented here is an extreme yet simple illustration of such an architecture. It has only one instruction, move memory to memory, yet it is useful.