Analysis of the conditional skip instructions of the HP precision architecture
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Increasing memory bandwidth with wide buses: compiler, hardware and performance trade-offs
ICS '97 Proceedings of the 11th international conference on Supercomputing
Subword Parallelism with MAX-2
IEEE Micro
Loop Transformation Using Nonunimodular Matrices
IEEE Transactions on Parallel and Distributed Systems
64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Journal of Signal Processing Systems
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