The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
Hardware/software tradeoffs for increased performance
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Empirical analysis of the mesa instruction set
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Towards better instruction sets
ACM SIGMICRO Newsletter
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This keynote address contains a brief account of the arguements being advanced in favor of reduced instruction sets. These arguements have relevance both to single chip computers and to larger computers. Some comments are made on instruction set design from a compiler writer's point of view, and on the advantages to be gained from regarding the design of an instruction set and the code generator of the compiler as a single task.