The ZS-1 central processor

  • Authors:
  • J. E. Smith;G. E. Dermer;B. D. Vanderwarn;S. D. Klinger;C. M. Rozewski

  • Affiliations:
  • Astronautics Corporation of America, Madison, WI;Astronautics Corporation of America, Madison, WI;Astronautics Corporation of America, Madison, WI;Astronautics Corporation of America, Madison, WI;Astronautics Corporation of America, Madison, WI

  • Venue:
  • ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
  • Year:
  • 1987

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Abstract

The Astronautics ZS-1 is a high speed, 64-bit computer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture, which splits instructions into two streams---one for fixed point/memory address computation and the other for floating point operations. The two instruction streams are then processed in parallel. Pipelining is also used extensively throughout the ZS-1.This paper describes the architecture and implementation of the ZS-1 central processor, beginning with some of the basic design objectives. Descriptions of the instruction set, pipeline structure, and virtual memory implementation demonstrate the methods used to satisfy the objectives. High performance is achieved through a combination of static (compile-time) instruction scheduling and dynamic (run-time) scheduling. Both types of scheduling are illustrated with examples.