Decoupling integer execution in superscalar processors

Authors:
Subbarao Palacharla;J. E. Smith
Affiliations:
Computer Sciences Department, University of Wisconsin-Madison, Madison, WI;Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI
Venue:
Proceedings of the 28th annual international symposium on Microarchitecture
Year:
1995

The ZS-1 central processor

ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
The CRAY-1 computer system

Communications of the ACM - Special issue on computer architecture
Decoupled access/execute computer architectures

ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture

Exploiting idle floating-point resources for integer execution

PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Improving Latency Tolerance of Multithreading through Decoupling

IEEE Transactions on Computers
Dynamic Code Partitioning for Clustered Architectures

International Journal of Parallel Programming
A Criticality Analysis of Clustering in Superscalar Processors

Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Exploiting idle register classes for fast spill destination

Proceedings of the 22nd annual international conference on Supercomputing
SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip

CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Sabrewing: A lightweight architecture for combined floating-point and integer arithmetic

ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers

Hi-index	0.00