A Simulation Study of Decoupled Architecture Computers
IEEE Transactions on Computers
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A comparison of dynamic branch predictors that use two levels of branch history
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
The agree predictor: a mechanism for reducing negative branch history interference
Proceedings of the 24th annual international symposium on Computer architecture
An analysis of correlation and predictability: what makes two-level branch predictors work
Proceedings of the 25th annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
The program decision logic approach to predicated execution
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
A scalable front-end architecture for fast instruction delivery
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Control CPR: a branch height reduction optimization for EPIC architectures
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Decoupled access/execute computer architectures
ACM Transactions on Computer Systems (TOCS)
Dynamic Branch Decoupled Architecture
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Hardware support for software controlled multithreading
ACM SIGARCH Computer Architecture News
An integrated partitioning and scheduling based branch decoupling
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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Branches are one of the main impediments to achieving maximum instruction-level parallelism. Branch prediction along with speculative execution is the main, incumbent methodology to hide branch stalls. Branch decoupled architectures offer an alternate way of reducing branch penalty. This paper presents a combination of the two methodologies, to show that they can coexist and may provide better performance than processors with conventional branch prediction techniques, but equivalent hardware resources. A trace based evaluation is presented, and with three different branch prediction techniques, it is shown that over twelve of the SPEC '95 CPU benchmarks, speculative branch decoupling performs significantly better than branch prediction with speculative execution, in all the cases. Since a trace-based approach has its limitations, the study is a limited one, but makes a strong case for further research in this area.