Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Cache coherence directories for scalable multiprocessors
Cache coherence directories for scalable multiprocessors
The Stanford FLASH multiprocessor
ISCA '94 Proceedings of the 21st annual international symposium on Computer architecture
The performance impact of flexibility in the Stanford FLASH multiprocessor
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Run-time spatial locality detection and optimization
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
IEEE Transactions on Computers
Computer Structures: Principles and Examples
Computer Structures: Principles and Examples
Computer Engineering; A DEC View of Hardware Systems Design
Computer Engineering; A DEC View of Hardware Systems Design
Mechanisms for distributed shared memory
Mechanisms for distributed shared memory
Design of a Computer—The Control Data 6600
Design of a Computer—The Control Data 6600
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This paper proposes a design for a fully programmable bus/memory controller. It enumerates the various advantages of such a controller, and demonstrates how modern memory models, common processor applications, and evolving operating system utilities point towards the use of the programmable controller as the next step forward in computer architecture. It also aims to evaluate the concerns that such a controller must take. Finally, It addresses a number of possible applications of a programmable controller, giving qualitative and quantitative analysis and sample implementations of several applications.