An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
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Conventional instruction issuing methods use hardware control mechanism to issue instructions in multiple-functional-unit systems. They reach physical limitations due to the complexity of issuing logic when they intend to issue multiple instructions per cycle. A new method, I-NET, is presented in this paper to overcome this shortcoming. I-NET uses a post-compiler to detect the data dependencies among instructions. The detected data dependence is then attached to the instruction code to form an instruction unit which can be executed independently with one another. These “pre-decoded” instruction units are fetched from the memory and sent to functional units directly. It achieve a maximal instruction issuing rate by avoiding a lengthy decoding procedure in the hardware. The performance study has shown I-NET to be a very promising method in exploring massive parallelism of a program in a multiple-functional-unit system.