Maurer computers for pipelined instruction processing†

Authors:
J. a. Bergstra;C. a. Middelburg
Affiliations:
Programming research group, university of amsterdam, p.o. box 41882, 1009 db amsterdam, the netherlands and department of philosophy, utrecht university, p.o. box 80126, 3508 tc utrecht, the nethe ...;Programming research group, university of amsterdam, p.o. box 41882, 1009 db amsterdam, the netherlands email: c.a.middelburg@uva.nl
Venue:
Mathematical Structures in Computer Science
Year:
2008

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Abstract

We model micro-architectures with non-pipelined instruction processing and pipelined instruction processing using Maurer machines, basic thread algebra and program algebra. We show that stored programs are executed as intended with these micro-architectures. We believe that this work provides a new mathematical approach to the modelling of micro-architectures and the verification of their correctness and the anticipated speed-up results.