The design of a RISC based multiprocessor chip

Authors:
Rajiv Gupta;Michael Epstein;Michael Whelan
Affiliations:
Dept. of Computer Science, Alumni Hall, University of Pittsburgh, Pittsburgh, PA;Philips Laboratories, North American Philips Corporation, 345 Scarborough Road, Briarcliff Manor, NY;Philips Laboratories, North American Philips Corporation, 345 Scarborough Road, Briarcliff Manor, NY
Venue:
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Year:
1990

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Abstract

This paper describes the architecture of a RISC based multiprocessor chip. The processors operate in a MIMD fashion executing parallel instruction streams generated by a parallelizing compiler for the exploitation of fine-grained parallelism. Low cost synchronization mechanisms are supported in hardware. The resulting system is tolerant of unpredictable delays in the progress of individual streams. Instruction level parallelism is exploited through the use of register channels and a mechanism for the collective branching of processors. For efficient synchronization during parallel execution of loops, fuzzy barriers are provided. On chip memory is organized into multiple banks in order to provide sufficient bandwidth for the processors. The RISC processors are based upon the Sun SPARC architecture.