Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
URPR—An extension of URCR for software pipelining
MICRO 19 Proceedings of the 19th annual workshop on Microprogramming
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
Compaction with General Synchronous Timing
IEEE Transactions on Software Engineering
Towards a microprogramming language schema
MICRO 11 Proceedings of the 11th annual workshop on Microprogramming
An improvement of trace scheduling for global microcode compaction
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
A retargetable compiler for a high-level microprogramming language
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
A model of clocked micro-architectures for firmware engineering and design automation applications
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
An axiomatization of low-level parallelism in microarchitectures
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Retargetable code generation and optimization using attribute grammars
Retargetable code generation and optimization using attribute grammars
Design and construction of a virtual machine resource binding language
Design and construction of a virtual machine resource binding language
Local code generation and compaction in optimizing microcode compilers
Local code generation and compaction in optimizing microcode compilers
A critical analysis of the global optimization problem for horizontal microcode (phase-coupled, compaction, code motion, compilation)
Trace selection for compiling large C application programs to microcode
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
A data-flow driven resource allocation in a retargetable microcode compiler
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
IMPACT: an architectural framework for multiple-instruction-issue processors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Comparing static and dynamic code scheduling for multiple-instruction-issue processors
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Generating compilers for generated datapaths
EURO-DAC '94 Proceedings of the conference on European design automation
Motivation and framework for using genetic algorithms for microcode compaction
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
IMPACT: an architectural framework for multiple-instruction-issue processors
25 years of the international symposia on Computer architecture (selected papers)
Motivation and framework for using genetic algorithms for microcode compaction
ACM SIGMICRO Newsletter
The use of traces for inlining in java programs
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
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We discuss the integration of a trace scheduling optimizer into a retargetable optimizing microcode compiler that handles complex timing relations. The trace scheduler requires no special treatment when retargeting the compiler, being constructed from machine independent algorithms that extract target micro-architecture details from a machine description used by the other compiler processes. We focus on the machine independent basis of the trace scheduler and demonstrate it on a hypothetical micro-architecture.