Trace-Based runtime instruction rescheduling for architecture extension

Authors:
YuXing Tang;Kun Deng;HongJia Cao;XingMing Zhou
Affiliations:
School of Computer, National University of Defense Technology, China;School of Computer, National University of Defense Technology, China;School of Computer, National University of Defense Technology, China;School of Computer, National University of Defense Technology, China
Venue:
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Year:
2005

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Abstract

The update of embedded processor may introduce new function unit, new coprocessor, or even new additional DSP. In many cases, software application can’t be fully rebuilt to utilize these new resources. This paper describes a novel framework, called Runtime Instruction Rescheduling (RIR), to solve this problem. RIR can find hot spots in binary codes, build a large instruction window to generate trace, reschedule and optimize instructions in traces. Different scheduling policies have been simulated. Shown from detailed simulation, RIR helps the old binary codes benefit from new hardware resources.