Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Design of the IBM RISC System/6000 floating-point execution unit
IBM Journal of Research and Development
Single instruction stream parallelism is greater than two
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Elements of information theory
Elements of information theory
Limits of control flow on parallelism
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Dynamic dependency analysis of ordinary programs
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
The multiscalar architecture
Value locality and load value prediction
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
The performance potential of data dependence speculation & collapsing
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Effects of communication latency, overhead, and bandwidth in a cluster architecture
Proceedings of the 24th annual international symposium on Computer architecture
Dynamic speculation and synchronization of data dependences
Proceedings of the 24th annual international symposium on Computer architecture
Proceedings of the 24th annual international symposium on Computer architecture
The predictability of data values
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Highly accurate data value prediction using hybrid predictors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Multipath execution: opportunities and limits
ICS '98 Proceedings of the 12th international conference on Supercomputing
Memory dependence prediction using store sets
Proceedings of the 25th annual international symposium on Computer architecture
Understanding the differences between value prediction and instruction reuse
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
A dynamic multithreading processor
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Storageless value prediction using prior register values
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Value prediction for speculative multithreaded architectures
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Reducing Memory Latency via Read-after-Read Memory Dependence Prediction
IEEE Transactions on Computers
Recycling waste: exploiting wrong-path execution to improve branch prediction
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Global Context-Based Value Prediction
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Efficacy and Performance Impact of Value Prediction
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
In Search of Speculative Thread-Level Parallelism
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Exploring Last n Value Prediction
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 30th annual international symposium on Computer architecture
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Memory dependence prediction
Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism
IEEE Transactions on Computers
Detecting and Debugging Insecure Information Flows
ISSRE '04 Proceedings of the 15th International Symposium on Software Reliability Engineering
Multithreaded Value Prediction
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Reducing Branch Misprediction Penalty via Selective Branch Recovery
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
An empirical study of the strength of information flows in programs
Proceedings of the 2006 international workshop on Dynamic systems analysis
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Dynamic per-branch history length adjustment to improve branch prediction accuracy
Microprocessors & Microsystems
Transparent control independence (TCI)
Proceedings of the 34th annual international symposium on Computer architecture
Raksha: a flexible information flow architecture for software security
Proceedings of the 34th annual international symposium on Computer architecture
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
On the potential of latency tolerant execution in speculative multithreading
IFMT '08 Proceedings of the 1st international forum on Next-generation multicore/manycore technologies
Algorithms and tool support for dynamic information flow analysis
Information and Software Technology
Measuring the strength of information flows in programs
ACM Transactions on Software Engineering and Methodology (TOSEM)
A load-instruction unit for pipelined processors
IBM Journal of Research and Development
Improving performance through deep value profiling and specialization with code transformation
Computer Languages, Systems and Structures
Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value Prediction
ACM Transactions on Architecture and Code Optimization (TACO)
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Value prediction is a technique to increase parallelism by attempting to overcome serialization constraints caused by true data dependences. By predicting the outcome of an instruction before it executes, value prediction allows data dependent instructions to issue and execute speculatively, hence increasing parallelism when the prediction is correct. In case of a misprediction, the execution is redone with the corrected value. If the benefit from increased parallelism outweighs the misprediction recovery penalty, overall performance could be improved. Enhancing performance with value prediction therefore requires highly accurate prediction methods. Most existing general value prediction techniques are local and future outputs of an instruction are predicted based on outputs from previous executions of the same instruction. In this paper, we explore the possibility of introducing highly accurate general correlating value predictor using dynamic information flow analysis. We use information theory to mathematically prove the validity and benefits of correlating value predictors. We also introduce the concept of linear value predictors, a new technique that predicts a new value from another one using a linear relation. We then conduct empirical analysis using programs from SPECjvm2008 and Siemens benchmarks. Our empirical measurements support our mathematical theory and allow us to make important observations on the relation between predictability of data values and information flow. Furthermore, we provide a scheme to select highly predictable variables, and explain when a specific value predictor can perform well and even outperform other predictors. Using a dynamic information flow analysis tool called DynFlow, we show that the values of a set of selected variables can be predicted with very high accuracy, up to 100%, from previous history of the same variables or other variables that have strong information flow into the predicted variable.