A timed HW/SW coemulation technique for fast yet accurate system verification

Authors:
Hoeseok Yang;Youngmin Yi;Soonhoi Ha
Affiliations:
School of EECS, Seoul National University, Seoul, Korea;Dept. of EECS, University of California, Berkeley, CA;School of EECS, Seoul National University, Seoul, Korea
Venue:
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Year:
2009

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Abstract

In System-on-chip (SoC) design, it is essential to verify the correctness of design before a chip is fabricated. While conventional hardware emulators validate functional correctness of hardware components quickly, only a few researches exist to use hardware emulators for timing verification since synchronization between the hardware emulator and the other parts easily overwhelms the gain of hardware emulator. In this paper we propose a novel hardware/software coemulation framework for fast yet accurate system verification based on the virtual synchronization technique. For virtual synchronization, interface protocol and interface logic between a hardware emulator and the HW/SW coemulation kernel are proposed. Experiments with real-life examples prove the effectiveness of the proposed technique.