MC-Sim: an efficient simulation tool for MPSoC designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Power reduction of CMP communication networks via RF-interconnects
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Applications driving 3D integration and corresponding manufacturing challenges
Proceedings of the 48th Design Automation Conference
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One of the key benefits of the scaling of CMOS is that the switching speed of the transistor improves over each technology generation. According to ITRS, fT and fmax, will be 600GHz and 1 THz, respectively, in 16nm CMOS technology. With the advance in CMOS mm-wave circuits, hundreds of GHz bandwidth will be available in the near future. In addition, compared with CMOS repeaters charging and discharging the wire, EM waves travel in a guided medium at the speed of light which is about 10ps/mm on silicon substrate. The question here is: How can we utilize over hundreds of GHz of bandwidth in a future mobile system through RF-I while concurrently achieving ultra-low power operation and dynamic allocation in bandwidth to meet future Network-on-Chip needs?