Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Networks on Chip: A New Paradigm for Systems on Chip Design
Proceedings of the conference on Design, automation and test in Europe
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An Analytical Performance Model for the Spidergon NoC
AINA '07 Proceedings of the 21st International Conference on Advanced Networking and Applications
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NoC Topologies Exploration based on Mapping and Simulation Models
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
Proceedings of the 12th annual conference on Genetic and evolutionary computation
Adaptive inter-layer message routing in 3D networks-on-chip
Microprocessors & Microsystems
Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture
Journal of Parallel and Distributed Computing
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We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in literature obtaining an optimized use of the channels of the network. This optimization allows to reduce the number of channels actually implemented on the chip while maintaining similar performances achieved by the two basic algorithms. In the second part of this paper, we propose a variation on the Spidergon's router architecture that enhances the performance of the network especially when the aEqualized routing algorithm is adopted.