Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Operating-system controlled network on chip
Proceedings of the 41st annual Design Automation Conference
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring programming model-driven QoS support for NoC-based platforms
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Enabling dynamic and programmable QoS in SoCs
Proceedings of the Third International Workshop on Network on Chip Architectures
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Costs and benefits of flexibility in spatial division circuit switched networks-on-chip
Proceedings of the Sixth International Workshop on Network on Chip Architectures
Microprocessors & Microsystems
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Predictability of multi-processor systems-on-chip communication is critical and needs to be addressed by providing the right mix of soft and hard real-time guarantees. To this end, state-of-the-art packet-switched networks-on-chip (NoC) provide different levels of quality-of-service (QoS) such as best effort (BE) and guaranteed throughput (GT). Unfortunately, GT resources have to be reserved for the worst-case, resulting in over-allocated resources. We introduce the SuperGT NoC, a packet-switched NoC that, besides BE and GT, supports a new SuperGT QoS. A SuperGT connection combines guaranteed and non guaranteed traffic while maintaining in-order packet delivery. Time-slots are allocated to provide guarantees and extra BE resources are claimed by injecting data during free slots. Simulation results demonstrate the advantages of SuperGT over GT. Synthesis results of the SuperGT virtual channel manager show that the SuperGT router is an inexpensive enhancement to state-of-the-art packet-switched NoCs.