Guaranteeing the quality of services in networks on chip
Networks on chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
HIBI Communication Network for System-on-Chip
Journal of VLSI Signal Processing Systems
Introducing the SuperGT network-on-chip: SuperGT QoS: more than just GT
Proceedings of the 44th annual Design Automation Conference
System-level Performance Verification of Multicore Systems-on-Chip
MTV '09 Proceedings of the 2009 10th International Workshop on Microprocessor Test and Verification
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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While System-on-Chip (SoC) complexity grows, the problem of designing interconnects offering a suitable Quality-of-Service (QoS) becomes drastically complex and forces designers to spend significant effort and time. Moreover, the current trend to employ SoCs in more and more different application scenarios requires solutions allowing applications' developers to program specific performance requirements. In this paper we propose an approach to implement a dynamic end-to-end QoS in Network-on-Chip as well as in circuit-switched or hybrid interconnects. Our solution is based on a low-cost hardware component that measures performance and automatically adapts traffic parameters to satisfy requirements. This self-adapting mechanism enables to easily re-program QoS by exposing a small set of registers to the software. Simulations results show that our dynamic approach achieves an accurate bandwidth control and significantly outperforms basic priority-based QoS solutions.