Control and Observation Structure for Analog Circuits with Current Test Data
Journal of Electronic Testing: Theory and Applications
Toward a scalable test methodology for 2D-mesh Network-on-Chips
Proceedings of the conference on Design, automation and test in Europe
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
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In multi-million gate devices, the number of required test patterns may be beyond the limits of current external automatic test equipment (ATE) capabilities. Besides, excessive number of production test vectors results in prohibitive test time that increases the test cost and decreases the production capacity. This paper introduces a new technique to test multiple identical blocks in parallel. The proposed technique can be used either in conjunction with ATE or as a stand-alone BIST technique to test multiple identical blocks on the same chip. The test time and the number of test patterns for testing multiple blocks is only a little bit higher than what is required for testing one block.