Robust concurrent online testing of network-on-chip-based SoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Much current research has focused on employing Network-on-Chips (NoC's) for communication among numerous cores on large scale SoC's. One side benefit of such designs is the potential to utilize this communication infrastructure with little modification for manufacturing test delivery. In this paper we present a test scheduling approach for such designs that minimizes test time through high-speed test delivery over the network and lower rate test execution at the target cores. To achieve this, test data are interleaved over the network in a time division multiplexed (TDM) approach. Experimental results with the ITC'02 SoC benchmarks are proposed that show substantial test time reduction beyond single speed techniques. Further enhancements are presented that overcome some deficiencies in the simplest approach.