On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
Buffering global interconnects in structured ASIC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the same prefabricated device and wire masks. Nevertheless, the interconnection delay in a pre-fabricated wire slows down circuit performance as a result of high capacitive load. We propose a dual-rail routing architecture that reduces wire delay by 10% to 15% compared to the original routing architecture. Furthermore, we propose a dual-rail insertion algorithm to reduce routing area overhead. The experimental results demonstrate that our dual-rail technique reduces wire delay by 9.8% with 4.8% routing area overhead and improves overall circuit performance by 7.0%.