FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
An architectural exploration of via patterned gate arrays
Proceedings of the 2003 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
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In this paper we compare the routing architecture of island-style FPGAs based on field-programmable switch boxes with a mask-programmable routing structure, in order to assess its position in the design space of routing opportunities available to VLSI IC designers. Although the results presented in this work depend on a few implementation details that will be discussed in the paper, the mask-programmable routing structure shows a large area saving and delay improvement with respect to the field-programmable switch box. As a consequence, we believe that between the two bounds of the design space, i.e., ASICs and FPGAs, there are several hybrid architectural solutions trading off performances, power, area, and programmability, which in the future can be considered for different applications.