Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Using Bounds
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A variation tolerant subthreshold design approach
Proceedings of the 42nd annual Design Automation Conference
Efficient statistical timing analysis through error budgeting
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel clock distribution and dynamic de-skewing methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Delay sensing for long-term variations and defects monitoring in safety---critical applications
Analog Integrated Circuits and Signal Processing
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To compensate for the growing effect of process, temperature and voltage variations in digital ICs, several dynamic approaches have been proposed. These approaches require the use of capacitors to offset the effects of variations. Although MOSFET based capacitors are a natural choice, such capacitances vary significantly depending on the applied voltage. In this paper, we propose techniques to make the capacitance of MOSFET based capacitors relatively constant over the applied voltage. We study approaches that are based on gate as well as diffusion capacitors. We study the trade-off (in terms of capacitance variation, requirement of a bias voltage and area efficiency) of all the proposed schemes. Simulation results are presented for two process technologies. We show that by using our techniques the capacitance variation across applied voltage can be reduced from 75% down to 3% for a 70nm process technology.