Leakage current reduction using subthreshold source-coupled logic

Authors:
Armin Tajalli;Yusuf Leblebici
Affiliations:
Microelectronic Systems Laboratory, Swiss Federal Institute of Technology, Lausanne, Switzerland;Microelectronic Systems Laboratory, Swiss Federal Institute of Technology, Lausanne, Switzerland
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

Citing 2
Cited 1

Robust subthreshold logic for ultra-low power operation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Power Aware Design Methodologies

Power Aware Design Methodologies

Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits

Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power-delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power-delay performance of these two topologies is proposed.