Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
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The scaling of Cu/Low-k interconnects into the deep submicron (DSM) regime is characterized by a significant increase in resistance. This increase is caused by geometrical scaling of interconnect dimensions, the non-scalability of high resistivity diffusion barrier and the resistivity increase due to surface and grain-boundary scattering of charge carrying electrons. The resistance of interconnects impacts the delay of the circuits and consequently the performance of chips. We investigate the impact of this phenomenon on system level performance for low power and high performance applications. It results that (a) it is important to consider the resistivity increase early in design phase to maximize the performance of the chips and (b) it is possible to optimally trade-off between various metrics of interest such as clock frequency, chip energy and chip area by exploring the freedom in choosing different interconnect process technology options.