Constant Impedance Scaling Paradigm for Scaling LC transmission lines
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A design space exploration of transmission-line links for on-chip interconnect
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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Models of electrical interconnects, including inductance and skin effect, are reviewed. The models are used for estimating the performance of electrical interconnects, particularly related to delays, data rates, and power consumption for off-chip and on-chip interconnects and for clock distribution. It is demonstrated that correctly utilized, electrical interconnects do not severely limit chip or circuit board capacity. Delays, data rates, and power consumption of electrical interconnects within a circuit board are acceptable and superior to optical alternatives.