Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
| Hi-index | 0.00 |
It is shown in this paper that contrary to the common conception, widening an on-chip interconnect wire will not cause the wire to behave as a lossless line. It is shown that the energy losses actually increase when widening a wire. The damping factor of the line, which determines the maximum bit rate that can be transmitted on a wire, also does not go to zero for wide wires as in lossless lines. This fact results in a serious physical limitation on the maximum bit rate that can be transmitted on a wire. It is shown that by increasing the cross-sectional width of an interconnect wire, the damping factor will saturate to a certain limit. An expression for this minimum damping factor for very wide wires is derived from fundamental physical constants and used to introduce an expression for the maximum bit rate that can be reached by widening an interconnect wire for a certain technology. It is shown that for current technology numbers, the maximum bit rate on a wire can be quite limiting for longer wires and that scaling trends will even decrease more this maximum bit rate, posing a serious limitation.