Wire Length Distribution Model Considering Core Utilization for System on Chip

Authors:
Takanori Kyogoku;Junpei Inoue;Hidenari Nakashima;Takumi Uezono;Kenichi Okada;Kazuya Masu
Affiliations:
Tokyo Institute of Technology;Tokyo Institute of Technology;Tokyo Institute of Technology;Tokyo Institute of Technology;Tokyo Institute of Technology;Tokyo Institute of Technology
Venue:
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Year:
2005

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Abstract

This paper presents a new model to estimate wire length distribution (WLD) of system on chip (SoC). The WLD represents a correlation between wire length and the number of interconnect, and we can predict power consumption, maximum clock frequency, chip size, etc with the WLD. The proposed model provides a WLD considering each core utilization of several macro blocks in a system LSI. We present an optimization method to determine each core utilization.