On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
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Networks on chips (NoCs) are emerging as a new paradigm for on-die communications in nanoscale integrated systems. Modules in a NoC-based digital system-on-chip exchange data (encoded as packets of bits) over a shared communication network within the chip. The network is constructed from multiple point-to-point data links interconnected by routers, such that messages can be relayed from any source module to any destination module via several multiplexed links. This talk begins by comparing NoC with traditional VLSI interconnect schemes. The wires in the links of a NoC are shared efficiently by many different signals. This sharing allows a relatively small number of physical wires to serve in lieu of many logical nets. A high level of parallelism is achieved, because all links in the NoC can operate simultaneously on different data packets. Therefore, as the complexity of integrated systems keeps growing, enabled by Moore's law, a NoC provides enhanced performance and scalability in comparison with previous communication architectures such as dedicated signal wires, shared buses, or segmented buses with bridges. In addition, NoCs can offer higher power-efficiency, increased engineering productivity and design modularity. The driving forces behind the current adoption of the NoC paradigm are discussed. From a physical design viewpoint, NoC links can simplify the task of designing wires for predictable speed, power, noise, reliability, etc., thanks to their regular, well controlled structure. From a system complexity viewpoint, with the advent of multi-core processor systems, required for achieving power efficiency, a network is a natural architectural choice. An NoC provides separation between computation and communication. It supports modularity and reuse of functional blocks via standard interfaces. The network can handle synchronization issues, serve as a platform for system test, and, hence, increase engineering productivity. Architectural considerations which are unique for on-chip network design are outlined. Although NoCs can borrow concepts and techniques from the well-established domains of computer networking and telecommunication infrastructure, it is impractical to directly apply standard solutions from these domains. In particular, NoC routers must be small, energy-efficient, and fast. The routing algorithms should be implemented by simple logic, and the number of data buffers should be minimal. Network topology may be application-specific. NoCs need to support 'quality of service,' namely achieve specific requirements in terms of throughput, end-to-end delays and deadlines for particular information flows. These issues define a large design space for NoCs, with interesting implications on the overall system design flow and tools. The talk concludes with an overview of practical approaches to NoC implementation, and an inventory of research problems which require solutions to enable broad acceptance of the NoC paradigm in actual practice.