Efficient representation of interconnection length distributions using generating polynomials
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
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The re-use of functional blocks within a large system on a chip (SoC) design results in a design trade-off between local intra-block and global inter-block communication. This paper develops a mathematical model to analyze the wire length distributions resulting from two possible layout strategies: the optimization of block terminal locations to minimizing global wire lengths which leave local wire lengths unoptimized, or the optimization of block terminal locations for minimizing local wire lengths which leave global wire lengths unoptimized. Results are presented for a model SoC floorplan composed of four identical functional blocks containing 12,769 cells and 245 terminals. Our analysis indicates that the best optimization strategy is dependent on the geometrical details of the floorplan with a local optimization producing smaller total wire lengths for a square (2 x 2) layout and global optimization producing lower total wire lengths for a linear (1 x 4) layout.