Delay variation tolerance for domino circuits

Authors:
Kai-Chiang Wu;Cheng-Tao Hsieh;Shih-Chieh Chang
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

Citing 7
Cited 0

Functional timing optimization

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Gate sizing using a statistical delay model

DATE '00 Proceedings of the conference on Design, automation and test in Europe
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Proceedings of the 39th annual Design Automation Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation

ITC '99 Proceedings of the 1999 IEEE International Test Conference
A methodology to improve timing yield in the presence of process variations

Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology

Proceedings of the 41st annual Design Automation Conference
Re-synthesis for delay variation tolerance

Proceedings of the 41st annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

Factors of delay variation, such as process variation and noise effects, may cause a manufactured chip to violate the pre-specified timing constraint. In this paper, we propose a novel re-synthesis technique to tolerate delay variation for domino circuits. Note that the slacks of nodes along critical paths are zero; any delay addition to those zero-slack nodes will worsen the final performance of a circuit. Our basic idea is to increase the slacks of nodes in the critical region by appending a redundant auxiliary sub-circuit to the original circuit. The auxiliary sub-circuit can cause critical paths to become false paths or imperceptible paths [7] so as to improve the capability of delay variation tolerance. Experimental results are very encouraging.